1. Field of the Invention
The present invention relates to technology for non-volatile storage.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Many types of EEPROM and flash memories utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series, sandwiched between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a top view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first (or drain) select gate 120 and a second (or source) select gate 122. Select gate 120 connects the NAND string to a bit line via bit line contact 126. Select gate 122 connects the NAND string to source line 128. Select gate 120 is controlled by applying the appropriate voltages to select line SGD. Select gate 122 is controlled by applying the appropriate voltages to select line SGS. Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate. For example, transistor 100 has control gate 100CG and floating gate 100FG. Transistor 102 includes control gate 102CG and a floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0.
Note that although FIGS. 1 and 2 show four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
A typical architecture for a flash memory system using a NAND structure will include several NAND strings. Each NAND string is connected to the source line by its source select gate controlled by select line SGS and connected to its associated bit line by its drain select gate controlled by select line SGD. Each bit line and the respective NAND string(s) that are connected to that bit line via a bit line contact comprise the columns of the array of memory cells. Bit lines are shared with multiple NAND strings. Typically, the bit line runs on top of the NAND strings in a direction perpendicular to the word lines and is connected to one or more sense amplifiers. The word lines (WL3, WL2, WL1 and WL0) comprise the rows of the memory array.
Each memory cell can store data (analog or digital). When storing one bit of digital data (referred to as a binary memory cell), the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data “1” and “0.” In one example of a NAND type flash memory, the threshold voltage is negative after the memory cell is erased, and defined as logic “1.” The threshold voltage after programming is positive and defined as logic “0.” When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate logic one is being stored. When the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell will not turn on, which indicates that logic zero is stored.
A memory cell can also store multiple levels of information (referred to as a multi-state memory cell). In the case of storing multiple levels of data, the range of possible threshold voltages is divided into the number of levels of data. For example, if four levels of information is stored (two bits of data), there will be four threshold voltage ranges assigned to the data values “11”, “10”, “01”, and “00.” In one example of a NAND type memory, the threshold voltage after an erase operation is negative and defined as “11”. Positive threshold voltages are used for the data states of “10”, “01”, and “00.” If eight levels of information is stored (three bits of data), there will be eight threshold voltage ranges assigned to the data values “000”, “001”, “010”, “011” “100”, “101”, “110” and “111”. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. For example, U.S. Pat. No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, both of which are incorporated herein by reference in their entirety, describe various data encoding schemes for multi-state flash memory cells. In one embodiment, data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a floating gate erroneously shifts to its neighboring physical state, only one bit will be affected.
Relevant examples of NAND type flash memories and their operation are provided in the following U.S. patents/patent applications, all of which are incorporated herein by reference: U.S. Pat. No. 5,570,315; U.S. Pat. No. 5,774,397; U.S. Pat. No. 6,046,935; U.S. Pat. No. 6,456,528; U.S. Pat. Publication No. US2003/0002348; and U.S. Pat. Publication No. 2006/0140011. The discussion herein can also apply to other types of flash memory in addition to NAND as well as other types of non-volatile memory.
When programming a flash memory cell, a program voltage is applied to the control gate and the bit line is grounded. Due to the voltage differential between the channel of the flash memory cell and the floating gate, electrons from the channel area under the floating gate are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised.
In some implementations, the programming voltage is applied as a series of voltage pulses. Each programming pulse is followed by one or more verify operations to determine if the memory cells has been programmed to the desired state.
Modern flash memory devices, particularly those of the NAND architecture and involving multi-state memory cells, are arranged in blocks and pages. A block refers to a unit of erase, and defines a group of memory cells that are simultaneously erased in a single erase operation. Typically, a block of memory cells is the smallest group of memory cells that can be erased. A page refers to a unit of programming, and defines a group of data bits (could be memory cells) that are simultaneously programmed. Each block typically includes multiple pages. Generally, the arrangement of memory cells into pages and blocks is based on the physical realization of the memory array. For example, in many NAND memory arrays, a page of memory cells is defined by those cells that share the same word line, and a block is defined by those pages residing in the same NAND string. For example, if a NAND string includes thirty-two memory cells in series, a block will typically include thirty-two pages, or an integer multiple of thirty-two pages. In some NAND memory arrays one word line can be shared by memory cells for two pages; the data for a first page is stored in the memory cells of even-numbered columns, while the data for a second page is stored in the memory cells of odd-numbered columns along that word line. Other arrangements are also possible.
In some memory systems utilizing multi-state memory cells, each bit of data in a memory cell is in a different page. For example, if an array of memory cells store three bits of data (eight states or levels of data) per memory cell, each memory cell stores data on three pages with each of the three bits being on a different page. Thus, within a block in this example, each word line is associated with three pages or an integer multiple of three pages. Other arrangements are also possible.
Historically, the organization of data stored in a flash memory has followed the file systems used in connection with magnetic disk storage, which stores data in sectors. A sector is typically a group of data of a fixed size, for example, 512 bytes of user data plus some number of bytes of overhead. In many modern file systems, the operating system of the computer or other host system arranges data into sectors, and writes data to and reads data from non-volatile storage on a sector-by-sector basis. To permit convenient use of flash memory devices in such systems and applications, many modern flash memories handle data in a similar fashion, mapping logical sector addresses to physical addresses in the flash memory array.
In recent years, the sizes and capacities of flash memory devices have greatly increased, resulting in memory arrays of more than 4 billion cells. In such arrays, a single word line may extend to over tens of thousands of memory cells. In such large scale flash memories, each page includes multiple sectors. As such, the units of data handled by the host system (i.e., “sectors”) are smaller than the smallest programming unit in the flash memory device. Typically, however, the multiple sectors of data that comprise a page of the flash memory will be sequentially communicated to the flash memory, and will be simultaneously programmed into a page of the flash memory in a single operation.
By way of further background, the use of error correction coding (ECC) in mass data storage devices and storage systems, as well as in data communications systems, is well known. As fundamental in this art, error correction coding involves the storage or communication of additional bits (commonly referred to as parity bits, code bits, checksum digits, ECC bits, etc.) that are determined or calculated from the “payload” (or original data) data bits being encoded. For example, the storage of error correction coded data in a memory resource involves the encoding of one or more code words that include the actual data and the additional code bits, using a selected code. Retrieval of the stored data involves the decoding of the stored code words according to the same code as used to encode the stored code words. Because the code bits “over-specify” the actual data portion of the code words, some number of error bits can be tolerated, without any loss of actual data evident after decoding.
Many ECC coding schemes are well known in the art. These conventional error correction codes are especially useful in large scale memories, including flash (and other non-volatile) memories, because of the substantial impact on manufacturing yield and device reliability that such coding schemes can provide, allowing devices that have a few non-programmable or defective cells to be useable. Of course, a tradeoff exists between the yield savings and the cost of providing additional memory cells to store the code bits (i.e., the code “rate”). Some ECC codes for flash memory devices tend to have higher code rates (i.e., a lower ratio of code bits to data bits) than the codes used in data communications applications (which may have code rates as low as ½). Examples of well-known ECC codes commonly used in connection with flash memory storage include Reed-Solomon codes, other BCH codes, Hamming codes, and the like. Typically, the error correction codes used in connection with flash memory storage are systematic, in that the data portion of the eventual code word is unchanged from the actual data being encoded, with the code or parity bits appended to the data bits to form the complete code word.
The particular parameters for a given error correction code include the type of code, the size of the block of actual data from which the code word is derived, and the overall length of the code word after encoding. For example, a typical BCH code applied to a sector of 512 bytes (4096 bits) of data can correct up to four error bits, if at least 60 ECC or parity bits are used. Reed-Solomon codes are a subset of BCH codes, and are also commonly used for error correction. For example, a typical Reed-Solomon code can correct up to four errors in a 512 byte sector of data, using about 72 ECC bits. In the flash memory context, error correction coding provides substantial improvement in manufacturing yield, as well as in the reliability of the flash memory over time.
By way of further background, the programming and erasing of conventional flash memory devices may involve the verification of the state of the memory cells being programmed or erased to ensure that the desired state has been reached for each of the cells subject to the operation. Indeed, considering that the programming and erasing of flash memory cells are typically performed by the application of a sequence of pulses of the appropriate voltages, and also considering that the pulse sequences consume substantial time and power, many flash memories now include verification operations during the programming or erasing operations themselves. For example, the programming of a page of memory cells is typically performed by applying a programming pulse, and then verifying the programmed cells against one or more desired “verify” voltages for the data level(s) being programmed. If not all of the memory cells verify to the appropriate desired level after a first pulse, the programming pulse is repeated (often at a higher voltage), and the cells are verified again. Upon all of the memory cells reaching the desired program level, the programming operation is terminated.
Verification is also typically performed in the erasing of a block of flash memory cells, with additional erase pulses applied as necessary to ensure all cells are erased. In general, for NAND flash memories, erase verification is typically performed by applying a selected control gate voltage to all of the word lines of the block being erased, to determine whether any of the cells conduct at that control gate voltage. Because the threshold voltages of erased cells are typically below 0 volts, and because the application of negative word line voltages is not desirable, the verifying of negative erase voltages is often done by way of a low or zero voltage on the word lines, with the common source lines biased to effectively place a negative gate-to-source voltage at each memory cell in the NAND chain. A similar approach is used during “soft” programming, which refers to the conventional operation of slightly programming erased flash memory cells, to prevent some or all of the cells from being too deeply erased.
A typical way of verifying programming is to test the conduction of each cell at a specific compare point that is set by a control gate voltage. Those cells that have previously been verified as sufficiently programmed are locked out, for example, by raising the bit line voltage for those cells in the page being programmed to a high level (e.g., the voltage of the Vdd power supply), to stop the programming process for those cells. Those cells that are not yet sufficiently programmed receive the next higher voltage pulse in the programming sequence, followed by another verify operation.
As is well known in this art, some memory cells are slower to program or erase than others, because of manufacturing variations among those cells, because those cells were previously erased to a lower threshold voltage than others, because of uneven wear among the cells within a page, or the like. And, of course, some cells cannot be programmed or erased whatsoever, because of a defect or other reason. As mentioned above, error correction coding provides the capability of tolerating some number of slow or failed cells, while still maintaining the memory usable. In some applications, a page of data is programmed by repeatedly applying programming pulses until all memory cells on that page verify to the desired programmed state. In these applications, programming terminates if a maximum number of programming pulses is reached prior to successful verifying of the programmed page, following which the number of cells that have not yet been verified to the desired state is compared with a threshold value, which depends on the capability of the error correction coding that will be used in the reading of data from that page. In other applications in which the error correction is sufficiently robust, programming and erasing time is saved by terminating the sequence of programming or erasing pulses upon the number of slow (or error) cells that are not yet fully programmed or erased being fewer than the number of bits that are correctable.
Error correction is typically performed on a sector-by-sector basis. Thus, each sector will have its own set of ECC codes. This error correction is convenient and useful because the sector is the desired unit of data transfer to and from the host system.
The usual maximum number of bits correctable within a sector of 512 bytes, using a BCH or Reed-Solomon code is four. Therefore, if a programming process results in two errors, the process can be considered successful because those two errors can be correct during a subsequent read process using ECC. In a page that stores 8 sectors, error correction should be able to tolerate 32 error bits (4 bits/sector×8 sectors). However, in conventional circuitry, the verification process counts errors (bits that have not properly programmed) across the entire page, regardless of the position of the error bit. Because it is possible that all error bits are within the same sector, the maximum number of error bits that can ignored during programming (or erase) verification over a page must be kept below the maximum number of allowed bits to ignore for a sector. Typically, in many memory systems, the maximum number of bits that can be ignored is even lower to ensure that some error correction remains to correct other errors found during the read process. Consider the example, where one bit has failed in each of eight sectors in a page. The typical system described above will not conclude that programming was successful, despite the ability of ECC to correct one error per sector.